In the design of a field effect transistor (FET) device, it is often desirable to increase the device's saturated drain-source current (I.sub.dss) without a corresponding decrease in the device's gate-to-drain breakdown voltage (BV.sub.gd0). However, a fundamental limitation in the design of a typical FET, such as a metal semiconductor FET (MESFET), is that breakdown voltage generally can only be increased at the expense of a lowered I.sub.dss. Similarly, Idss can generally only be increased at the expense of a lowered breakdown voltage.
One specific application in which it is desirable to increase breakdown voltage without a corresponding decrease in I.sub.dss is in radio frequency (RF) power MESFETs. Specifically, in such a MESFET it is desirable to have both high output power and low side band noise. High output power for such a device correlates directly to high Idss, and low side band noise correlates directly to high breakdown voltage. However, as discussed above, in existing MESFET devices it is difficult to increase breakdown voltage without a corresponding decrease in I.sub.dss.
Two typical types of MESFETs used in RF power applications are planar MESFETs and recessed-gate MESFETs. In a planar MESFET, the relationship between I.sub.dss and breakdown voltage can only be controlled by varying channel doping and source/drain electrode spacing. There is no other effective means for optimizing the device's breakdown voltage characteristics. Despite this limitation, though, planar self-aligned MESFET structures are commonly used and have the advantages of a self-aligned device and good control during manufacture.
A recessed-gate MESFET differs in structure from a planar MESFET and is used as an attempt to overcome the limitations of the inverse relationship between breakdown voltage and I.sub.dss. Simply stated, a recessed-gate MESFET is a device having its gate formed upon a recessed region in the active region of the device which is formed by a recess etch of the active region. The gate is recessed so that the electric field at the edges of the gate are reduced; this allows the breakdown voltage of the device to be increased without a decrease in I.sub.ss. Thus, the relationship between I.sub.dss and breakdown voltage can be controlled by channel doping, electrode spacing, and the recess etch depth. However, the process for fabricating a recessed-gate MESFET does not permit the use of self-aligned source/drain regions, which are desirable for achieving ever smaller device geometries, and the recess region itself is formed by removing a portion of the active area directly under the gate. This removal is disadvantageous because it leads to poor control of device parameters, such as I.sub.ss and threshold voltage, during manufacture.
Thus, it would be advantageous to have a structure for a FET device that improves BV.sub.gd0 without a corresponding decrease in I.sub.dss and that can be self-aligned with good process control of device characteristics.